1. The Field of the Invention
The present invention relates to metallization methods in the manufacture of microelectronic semiconductor devices. More particularly the present invention relates to methods of making microelectronic semiconductor devices having up to three-level interconnect structures of conductive materials in which a single deposition process is used.
2. The Relevant Technology
After fabrication of microelectronic devices in and upon semi-conductive substrate assemblies, metallization of the circuitry is required to place the microelectronic devices in electrical communication one to another according to design. Prior art designs called for contacts, trenches, and superficial wires for metallization. These designs may require three or more separate depositions of conductive material in order to complete metallization of the design. Each layer of conductive material was made by the steps of depositing the conductive layer, depositing and patterning a photoresist or equivalent, and etching the conductive layer.
With multiple depositions of conductive material, usually composed of a metal or a doped polysilicon, various technical challenges and device characteristics arise. As semiconductor manufacturing advances from very large scale integration (VLSI) to ultra-large scale integration (ULSI), the devices on a semiconductor wafer shrink to sub-micron dimensions, and the circuit density increases to several million transistors per die. In order to accomplish the required high device packing density, progressively smaller feature sizes have been required. These reduced feature sizes include the width and spacing of interconnecting lines in the service geometry thereof, such as comers and edges.
As features become smaller, a process flow that requires multiple depositions tends to narrow the process window for error in misalignments. As such, a single misalignment in metallization can cause a significant yield reduction.
One technical obstacle in metallization line formation is depth-of-field limits in photolithography. Formation of metallization lines follows contact plug filling by deposition and patterning of a deposited metallization material. When a contact plug is formed in a contact hole, the metallization material that fills the contact hole may have an irregular surface immeadiately below the contact hole due to the filling thereof. The irregular surface of the metallization material has depth-of-field focusing problems due to a rough topography thereof. The rough topography can cause photolithographic steps to produce irregular metallization line widths, which in turn lead to unpredictable resistances along the metallization lines and unreliable device speeds.
Another technical obstacle is the inherent resistance in metal-to-metal interfaces between contacts and trenches, contacts and metallization lines, and trenches and metallization lines. This obstacle arises when disparate metals make up the contact and metallization line, or even when metals of the same composition are poorly interfaced. The process of forming contacts in semiconductors and the subsequent wiring of those contacts to form a completed integrated circuit conventionally comprises two steps.
The first step comprises forming an aluminum or tungsten plug within a contact hole by such methods as, for example, cold or hot deposition, cold-slow, or hot-fast force filling, or metal reflow of the contact hole. There are other methods of hole filling with aluminum known in the art. Tungsten plug hole filling comprises depostion of selected adhesional and barrier liner layers, followed by CVD of tungsten. The contact hole is usually defined within an insulation layer. Next, a planarizing step leaves the titanium or tungsten plug electrically isolated in the contact hole. The second deposition step comprises forming a metallization line over the plug, where the metallization line is usually composed of a material different from that of the plug.
The plug interface with the metallization line is problematic to electrical conduction because completely connected interface areas are difficult to achieve, particularly in dissimilar metals. Because resistance in electrical conduction is a function of cross-sectional area through the conductive body, a less than completely connected interface between contact or trench and metallization line causes a higher resistance than a completely connected interface. In addition to incomplete interface connections, filling a contact hole with aluminum requires high temperatures and pressures that may cause large or irregular grain structures to grow. Large or irregular grain structures resist flow and etchback, and do not conduct current as well as fine-grained structures.
Still other technical obstacles are electromigration and metal creep. These involve the transport of metal atoms along the direction of electron flow in the conductive lines, and can lead to failure of the conductive lines. These obstacles are discussed below in turn.
Aluminum-copper electromigration is well established in a structure with an aluminum-copper metallization line interfacing with a titanium or tungsten plug. The phenomenon occurs because copper diffusivity through titanium or tungsten is much lower than copper diffusivity through aluminum. Therefore, the copper is depleted from the area of the titanium or tungsten plug by the current flow, leading to failure at the interface between the titanium or tungsten plug and the aluminum-copper line.
Metal creep, on the other hand, occurs due to differences in the thermal coefficients of expansion between metals, insulators, and silicon materials. Differences in thermal coefficients of expansion can build up stresses in the metal interconnects, which can lead to migration of atoms from one area to another. This migration of atoms forms voids or vacancies in the metal interconnect which cause can an electrical failure.
The problems of cumulative misalignments and of electrical resistance at metal-metal interfaces with its several destructive effects, are to be avoided. What is needed is methods of making multi-level interconnect structures that overcome these problems.